The present invention relates to a semiconductor package and a method for manufacturing the same.
These days, semiconductor packages capable of storing a large amount of data and processing stored data in a short amount of time is well known in the art.
Semiconductor packages are manufactured first through a semiconductor chip manufacturing process that integrates elements such as transistors, resistors and capacitors in a wafer for forming semiconductor chips. Second, semiconductor packages are manufactured through a packaging process for parting the semiconductor chips from the wafer, for electrically connecting the semiconductor chips with outside circuit boards, etc. and for protecting the semiconductor chips having inferior strength from externally applied shocks and/or vibrations.
Recently, as the packaging technologies are developed, a wafer level package, which has a size no greater than 100% to 105% of the size of a semiconductor chip, and a stacked semiconductor package, in which a plurality of semiconductor chips or a plurality of semiconductor packages are stacked, have been disclosed in the art.
The wafer level package provides advantages in that it has reduced volume and weight and can process data at a high speed.
In general, the wafer level package has redistribution line patterns which are connected with the bonding pads of a semiconductor chip, and includes an insulation layer which has openings for exposing portions of the redistribution line patterns. Solder balls or the likes are attached to the redistribution line patterns which are exposed through the openings of the insulation layer.
However, when manufacturing the wafer level package, in order to form the insulation layer having the openings for exposing the redistribution line patterns, it is necessary to implement a coating process for forming an insulation layer containing a photoresist material on a wafer, a lithographic process for exposing the insulation layer, and a development process for patterning the exposed insulation layer. As a result, a problem is caused in that the number of processes for manufacturing the wafer level package markedly increases.